1. Technical Field
This invention pertains to integrated circuits, and more specifically to an integrated circuit method and apparatus for providing a fully controllable internal clock which can be manipulated to allow an integrated circuit to run in different modes and at different speeds, and thereby provide more effective debugging of the integrated circuit.
2. Prior Art
Testing of very large scale integrated circuit (VLSI) devices is complex. Nevertheless, it is essential to verify that a given circuit functions properly in order to provide the end user with a system which will meet specified needs.
The internal clock is an essential and one of the most important parts of any synchronous VLSI chip. A fully controllable integrated circuit internal clock is very important in integrated circuit debugging. By manipulating the internal clock in different ways, an integrated circuit chip can be controlled to run in different modes and at different speeds during debug operations. These modes can be used either on the tester or in a system environment. Critical information about the state of the integrated circuit can be obtained from such clock manipulation.
Integrated circuit internal clocks are operated in the prior art according to the boundary scan test method. In the boundary scan test method, various test data is serially loaded into locations within the integrated circuit and then the integrated circuit is operated in a conventional fashion based upon the serially loaded data, and the resultant output data is verified. The boundary scan test method is described, for example, in "IEEE Standard Test Access Port and Boundary-Scan Architecture", IEEE STD 1149.1-1990 (also referred to herein as "IEEE 1149.1").
In IEEE 1149.1, it is specified that the clock input must be capable of being stopped at 0 indefinitely, without causing any change to the state of the test logic. The clock is stopped, for example, when a test system needs to fetch data from backup memory such as a disc.
One implementation of IEEE 1149.1 was incorporated into the microSPARC.TM. integrated circuit from Sun Microsystems, Inc., the assignee of this application, and was described in "microSPARC.TM.: A Case-Study of Scan Based Debug", IEEE International Test Conference, October 1994, pages 70-75. The microSPARC.TM. device takes a high-frequency waveform from either the on-chip phase locked loop (PLL) or the external clock input pins, and uses it to generate the internal clock waveforms as well as the sbclk waveform which clocks the external system bus. Under the control of on-chip register bits, which are accessible only by IEEE 1149.1 scan operations, clocks are started and stopped in a variety of ways, to facilitate debug and test. The microSPARC clock controller includes a simple 32-bit on-chip Extended Cycle Counter (XCC) for precise control of system clocking. The XCC is a simple binary counter, accessible only by scan, which increments on sbclk positive edges. To stop a clock in the microSPARC device, a stop clock CCR bit is set. To start the clock again, the start clock CCR bit is set. In the microSPARC.TM. device, a number of clock functions are supported, including a single step operation, in which a single clock pulse is generated, counting the number of clock cycles which have been issued between any two points in time, issuing a plurality of N clock pulses, stopping the clock on either external or internal events, or N cycles after an internal event, as well as on the nth clock cycle in which an internal event is detected.